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	<title>www.it-pruefungen.ch Prüfungsvorbereitung Prüfungsfragen &#187; AAE EN0-001</title>
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		<title>Prüfung Exam study guide EN0-001 Testfragen</title>
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				<category><![CDATA[ARM]]></category>
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		<description><![CDATA[Prüfung Exam study guide EN0-001 Testfragen ARM Accredited engineer www.it-pruefungen.ch QUESTION NO: 1 What view in a debugger displays the order in which functions were called? A. The Call Stack view B. The Memory view C. The Registers view D. The Variables &#8230; <a href="https://www.pruefungsfrage.ch/2018/08/23/pruefung-exam-study-guide-en0-001-testfragen/">Weiterlesen <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<p><a href="https://www.it-pruefungen.ch/EN0-001.htm">Prüfung Exam study guide EN0-001 Testfragen</a> ARM Accredited engineer www.it-pruefungen.ch</p>
<p>QUESTION NO: 1<br />
What view in a debugger displays the order in which functions were called?</p>
<p>A. The Call Stack view<br />
B. The Memory view<br />
C. The Registers view<br />
D. The Variables view</p>
<p>Answer: A</p>
<p>QUESTION NO: 2<br />
Printf statements could be used to achieve which of the following debug tasks?</p>
<p>A. Observe changes to a local variable in a function<br />
B. Capture a real-time trace of program execution<br />
C. Debug boot code, before a call to the C main() function<br />
D. Stop the processor at an interesting location in the code</p>
<p>Answer: A</p>
<p>QUESTION NO: 3<br />
When the processor is executing in Thumb state, which of the following statements is correct about the values stored in R15?</p>
<p>A. Bits[31:16] are duplicated with bits[15:0]<br />
B. The PC value is stored in bits[31:1] and bit[0] is treated as zero<br />
C. The PC value is stored in bits[31:16] and bits[15:0] are undefined<br />
D. The PC value is stored in bits[15:0] and bits[31:16] are undefined</p>
<p>Answer: B</p>
<p>EN0-001 Prüfungsfragen, EN0-001 Examensfragen ARM Accredited engineer (ICND2 v3.0) www.it-pruefungen.ch</p>
<p>QUESTION NO: 4<br />
A standard performance benchmark is being run on a single core ARM v7-A processor. The performance results reported are significantly lower than expected. Which of the following options is a possible explanation?</p>
<p>A. L1 Caches and branch prediction are disabled<br />
B. The Embedded Trace Macrocell (ETM) is disabled<br />
C. The Memory Management Unit (MMU) is enabled<br />
D. The Snoop Control Unit (SCU) is disabled</p>
<p>Answer: A</p>
<p>QUESTION NO: 5<br />
When setting the initial location of the stack pointer and the base address of the heap, the ARM EABI requires that the:</p>
<p>A. Base address of the heap must be the same as the initial stack pointer.<br />
B. Stack pointer must be 8-byte aligned.<br />
C. Heap must be in external RAM.<br />
D. Initial stack pointer must be the lowest addressable memory location.</p>
<p>Answer: B</p>
<p>Prüfungsvorbereitung Studienmaterial EN0-001 deutsch ARM Accredited engineer www.it-pruefungen.ch</p>
<p>QUESTION NO: 6<br />
In an ARMv7-A processor, which control register is used to enable the Memory Management Unit (MMU)?</p>
<p>A. The ACTLR<br />
B. The SCTLR<br />
C. The TTBCR<br />
D. The CONTEXTIDR</p>
<p>Answer: B</p>
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